# Superconducting quantum circuit of NOR in quantum annealing

### Features of NOR and NAND operation

NOR is known to be a versatile computing unit. In our method, the Hamiltonian is designed to minimize energy for logic components of NOR. The superconducting quantum circuit is constructed by directly implementing the Hamiltonian shown in Supplementary Fig. 1(a). Two kinds of samples are prepared consisting of three qubits, corresponding to *A* duck *B* for inputs and *R* for the logic result, with critical currents (*IN*_{c}) of 6.25 µA (NOR1) and 3.75 µA (NOR2). The sample configuration is described in the “Methods” section. The logic components of NOR, corresponding to the four combinations of (*A*, *B*, *R*) with the minimum energy, appear at a degeneracy point after QA. Theoretically, the degeneracy point is expressed as.

$$I_{h2} = frac{{M_{23} }}{{M_{31} }} cdot I_{h1}$$

,

$$I_{h3} = frac{{M_{1} }}{{M_{3} }} cdot frac{{M_{23} }}{{M_{12} }} cdot I_{h1 }$$

(1)

where *IN*_{hrsin} (*in* = 1–3) is the external bias of qubit *in*(corresponding to labels of *A* , *B,*duck *R* ), *M*_{in} (*in* = 1–3) is the mutual inductance between qubits *in*and the external bias line, and *M*_{ij} (*in*= 1–3, *j*= 1–3) is the mutual inductance between qubits *in*duck *j*. The process for deriving Eq. (1) is described in the Supplementary Methods. The inductances of the qubits and the mutual inductances between them are extracted from the circuit layout (see Methods). The theoretical degeneracy points of NOR1 and NOR2 are estimated as (*IN*_{h1}, *IN*_{h2}, *IN*_{h3}) = (1.4, 1.4, 3.1) and (1.3, 1.3, 2.8) [µA], respectively. Figure 1a-c respectively shows state diagrams obtained from theory, from simulation using a Josephson integrated circuit simulator (JSIM)^{27} with *IN*_{h3}= 2.0 µA, and from an experiment with *IN*_{h3}= 2.0 µA carried out at 10 mK. Detailed methods of the JSIM and the experiment are presented in the Methods section and in the “Experimental configuration” section of the Supplementary Methods, respectively. In the JSIM analysis, a thermal noise current is neglected in order to emphasize the trend of the boundary condition in each logic component. A degeneracy point, where every logic component in NOR appears, is found around a current condition of (*IN*_{h1}, *IN*_{h2} , *IN*_{h3} ) = (1.8, 1.8, 2.0) [µA] both in experiments and in JSIM analysis at NOR1. Supplementary Fig. 3 shows the frequency distribution of logic components in experiments carried out at the degeneracy point. Logic components corresponding to the minimum energy of the Hamiltonian are selectively generated. In the state diagram, the boundary along the diagonal direction is found, which we call “ladder” for the sake of convenience. The ladder rising diagonally in the left direction is generated when *IN*_{h3}decreases from the degeneracy point (Fig. 1d-f). On the other hand, the ladder rising diagonally in the right direction is generated when *IN*_{h3}increases from the degeneracy point (Fig. 1g-i). These trends agree qualitatively with theory, JSIM analysis, and experiments. At the experimentally obtained degeneracy point, the logic components of NOR randomly occur (see Supplementary Fig. 4 and the “Detailed characteristics of the NOR operation” section of the Supplementary Note). Note that we can produce a desirable logic component by applying an appropriate offset current (α) against the degeneracy point. For example, the logic component of (*A*, *B*) = (0, 1) can be considered by applying an external flux bias of (*IN*_{h1} ′, *IN*_{h2} ′) = (*IN*_{h1}— α, *IN*_{h2}+ α). This corresponds to adopting α along a diagonal direction from the degeneracy point. By applying an appropriate value of α, NOR logic can be reproduced with high accuracy (see Supplementary Fig. 5). We emphasize that a flux injection to one of the qubits by adopting α in the initial condition restricts the state of the other qubit because the qubits interact with each other to minimize the energy after QA. Moreover, this quantum circuit behaves as NAND when *IN*_{hrs}is supplied with a negative sign. In the state diagram of NAND, the absolute value of the degeneracy point is almost the same as that of NOR. The boundary of each logic component is modulated by *IN*_{h3,} as it similarly is in NOR (see Supplementary Fig. 6 and the “NAND operation” section of the Supplementary Note). Each logic component of NAND is reproduced with a probability of success up to 100% by adopting an appropriate value of α (see Supplementary Fig. 7). QA in NOR1 shows a high probability of success in NOR and NAND operation, but its degeneracy point is different among theory, JSIM analysis, and experiments.

### Gray zone evaluation

In NOR2, the barrier height in the energy potential of each qubit is reduced compared with that in NOR1 due to the reduction of *IN*_{c}. Supplementary Fig. 8 shows the frequency distribution of each logic component with a current condition of (*IN*_{h1}, *IN*_{h2} ) = (1.6, 1.6) [µA] and a modulation of *IN*_{h3}between 0 and 9 µA. Around an *IN*_{h3}of 2.8 µA, all candidate logic components in NOR occur. Figure 2a, b show state diagrams with 2D and 3D images at an *IN*_{h3}of 2.8 µA. The experimental degeneracy point is close to the theoretical one. Note that the boundary of each logic component drastically changes around this point. The experimental degeneracy point of NOR2 is (*IN*_{h1} , *IN*_{h2}, *IN*_{h3} ) = (1.6, 1.6, 2.8) [µA]. For the sake of convenience, we define the transient width between two different logic regions as a “gray zone.” Two types of gray zones exist: Type I is generated between neighboring regions, such as “100”- “001” and “001”- “010”, and Type II occurs in the same diagonal direction as the ladder. Theoretically, the width of the ladder monotonically decreases with external bias *IN*_{h3}before the degeneracy point. Later, it monotonically increases with *IN*_{h3}. Types I and II can be evaluated from four kinds of line profiles (L_{1} -L_{4}) and the two profiles L_{5} and L_{6} , respectively (Fig. 2c-f). In L_{5} and L_{6} , four logic components of NOR are identified. Type I gray zones depend on the annealing time (*T*_{a} ) (see Supplementary Fig. 9 and the “Feature of the Type I gray zone” section of the Supplementary Note). As *T*_{a} decreases, the spread of the gray zone becomes wider. With longer *T*_{a} , the effect of noise can be time-averaged. This contributes to the reduction of the gray zone, resulting in the use of the quantum annealing effect. These gray zones are clarified in the case of JSIM analysis with the thermal noise current (see Supplementary Fig. 10). Figure 3a, b show the Type I gray zones evaluated in experiments and in JSIM analysis, respectively. The minimum width of the gray zone differs between experiments and JSIM analysis. The impact of flux generated by surrounding circuits appears differently between JSIM and experiments, which results in a difference in the minimum width of the gray zone. However, the consideration of the equidistant current step in the evaluation of the gray zone contributes to suppressing the effect of minor logic component generation. Gray zones between “100” and “001” and between “001” and “010” tend to be large. These trends correspond to the fact that a boundary position is likely to change due to *IN*_{h3} in Fig. 1, indicating an ease in changing the energy state. On the other hand, the values are small in cases of boundaries between “110” and “010” and between “100” and “110”. These trends correspond to the fact that the values of *IN*_{h1} duck *IN*_{h2}do not change with modulation of *IN*_{h3}in Fig. 1, indicating difficulty in changing the energy state. These relationships are also confirmed regardless of the value of *T*_{a}(see Supplementary Fig. 9). Figure 3c, d show a Type II gray zone with two trends in experiments and JSIM analysis, respectively. The first is a monotonic response against the absolute value of *IN*_{h3}starting from the degeneracy point. This trend agrees with the prediction of the theory. The second is the gray zone spreading slightly wider with the decrease of *IN*_{h3}before the degeneracy point than with the increase of *IN*_{h3}after the degeneration point. These trends correspond to the result shown in Fig. 1, where occupation of the “001” region modulates widely with a decrease of *IN*_{h3}compared with the case of an increase of *IN*_{h3}. JSIM analysis also reproduces the same trends seen in experiments. Note that trends change for a thermal noise current above 2.5 pA/√Hz in JSIM analysis. Below 2.0 pA/√Hz, trapping to the local minimum state occurs (see the “Gray zone analysis in JSIM” section of the Supplementary Methods). The logic in NOR and NAND can be realized with high accuracy by tuning the current condition with values of α above 1 µA along a diagonal direction from the degeneracy point, contributing to the avoidance of the gray zone.